The present invention relates to a PLL circuit, a semiconductor device including the same, and a control method of a PLL circuit, and for example, relates to a PLL circuit, a semiconductor device including the same, and a control method of a PLL circuit, which are suitable for quickly locking a phase.
The PLL circuit is required to reduce jitter of an output clock signal as much as possible. A solution to such a requirement is disclosed in Japanese Patent No. 5448870.
The PLL circuit disclosed in Japanese Patent No. 5448870 includes a phase comparator that compares a reference signal with a feedback signal of an oscillation signal, first and second charge pumps, each of which outputs a current according to a comparison result of the phase comparator, an integrating filter that generates a first voltage signal by filtering a signal generated based on an output current of the first charge pump, a ripple filter that generates a second voltage signal by filtering a signal generated based on an output current of the second charge pump, a comparator that compares the first voltage signal generated by the integrating filter with a reference voltage, a second integrating filter that generates a third voltage signal by filtering a comparison result of the comparator, and a voltage controlled oscillation circuit that generates an oscillation signal of an oscillation frequency according to the first to the third voltage signals. Thereby, the PLL circuit can adjust an offset component of the oscillation frequency by the third voltage signal, so that it is considered that the PLL circuit can suppress increase of jitter of the oscillation signal (output clock signal).